As memory devices continue to scale, the power supply voltage (VDD) employed to power these devices is typically reduced. In some cases, a reduced VDD makes it more difficult to retain stored charge in memory devices such as static random access memories (SRAMs).
To improve the stability and performance of SRAM cells, a separate (higher) power supply voltage called VCS has been introduced in addition to the main chip power supply voltage VDD. This secondary, higher voltage VCS provides the voltage required to ensure proper charge storage within memory cells, while allowing the remainder of the devices on a memory chip to operate at a reduced VDD.
While use of a separate power supply voltage VCS may improve the charge storage characteristics of SRAMs, other device issues may arise. For example, VCS is typically held at a slightly higher voltage than the chip supply voltage VDD. For example, VCS may be about 100 mV to 200 mV higher than VDD in some cases. During device operation, however, VCS may occasionally spike to a higher voltage level, such as about 600 mV or higher above VDD. This may prevent transistors within the memory array from turning off, and cause the memory array to fail.
To reduce the affects of voltage spikes in VCS, level shifters may be employed to help separate the VCS and VDD voltage domains, and maintain an acceptable voltage differential between VCS and VDD. However, some prior art level shifters may generate extraneous currents that deleteriously affect memory array operation. Accordingly, a need exists for improved level shifter circuitry for use with memory arrays.